High-reliability fault-tolerant 16-MBit memory chip
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[1] Masaki Tsukude,et al. A speed-enhanced DRAM array architecture with embedded ECC , 1990 .
[2] K. Arimoto,et al. A built-in Hamming code ECC circuit for DRAMs , 1989 .
[3] Sunlin Chou,et al. Fault tolerant techniques for memory components , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[4] Howard Leo Kalter,et al. High-reliability fault-tolerant 16 Mbit memory chip , 1991, Annual Reliability and Maintainability Symposium. 1991 Proceedings.
[5] Howard Leo Kalter,et al. A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC , 1990 .
[6] C. H. Stapper,et al. High-speed on-chip ECC for synergistic fault-tolerance memory chips , 1991 .
[7] Toshio Yamada,et al. A 4-Mbit DRAM with 16-bit concurrent ECC , 1988 .
[8] Charles H. Stapper,et al. Synergistic Fault-Tolerance for Memory Chips , 1992, IEEE Trans. Computers.
[9] S. E. Schuster. Multiple word/bit line redundancy for semiconductor memories , 1978 .
[10] Pinaki Mazumder,et al. Design of a Fault-Tolerant DRAM with New On-Chip ECC , 1989 .
[11] J. C. Pickel,et al. Cosmic Ray Induced in MOS Memory Cells , 1978, IEEE Transactions on Nuclear Science.
[12] D. Horak,et al. A high performance 16-Mb DRAM technology , 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.
[13] J. Yamada. Selector-line merged built-in ECC technique for DRAMs , 1987 .
[14] T. May,et al. Alpha-particle-induced soft errors in dynamic memories , 1979, IEEE Transactions on Electron Devices.
[15] R.P. Cenker,et al. A fault-tolerant 64K dynamic random-access memory , 1979, IEEE Transactions on Electron Devices.
[16] Y. Taur,et al. A variable-size shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS , 1988, Technical Digest., International Electron Devices Meeting.
[17] A. Chen. Redundancy in LSI memory array , 1969 .
[18] John A. Fifield. A High-Speed On-Chip ECC System Using Modified Hamming Code , 1990, ESSCIRC '90: Sixteenth European Solid-State Circuits Conference.
[19] C. H. Stapper,et al. The evaluation of 16-Mbit memory chips with built-in reliability , 1992, 30th Annual Proceedings Reliability Physics 1992.
[20] T. Mano,et al. A submicron VLSI memory with a 4b-at-a-time built-in ECC circuit , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[21] K. Jenkins,et al. Ion microbeam probing of sense amplifiers to analyze single event upsets in a CMOS DRAM , 1991 .
[22] P. J. McNulty,et al. Soft Errors Induced by Energetic Protons , 1979, IEEE Transactions on Nuclear Science.
[23] R. R. O'Brien,et al. Collection of charge from alpha-particle tracks in silicon devices , 1983, IEEE Transactions on Electron Devices.