An integrated state assignment and flip-flop selection technique for FSM synthesis

Abstract In the automatic synthesis of Finite State Machines (FSMs), the state assignment and the choice of flip-flops significantly affect the cost of the combinational logic. To meet the demands of the increasing complexity of integrated circuits, we present an integrated state assignment and sequential element selection approach to synthesize area-efficient FSMs. The FSM synthesis approach is modeled as an optimization problem and is solved by using the guided evolutionary simulated annealing (GESA) technique. The GESA is a new type of parallel and distributed processing approach for searching the optimal solutions. Since the optimization problem at hand is NP-hard, a distributed algorithm for the GESA technique is developed and implemented on Network of Workstations (NOW) to speedup the search process. Promising speedups are obtained by running the distributed GESA algorithm on a NOW. Efficacy of the proposed technique is demonstrated by carrying out a comparison with other state-of-the-art techniques such as the MUSTANG, NOVA and JEDI for MCNC benchmarks. The proposed integrated state assignment and sequential element selection approach allows all types of flip-flops and offers considerable improvement in PLA area as compared to the existing techniques that use only D type flip-flops as the sequential element.