Boosting Multiprocessor Program Performance using Optimized Cache Coherence Protocols

While shared-memory multiprocessors emerge on the commercial arena as general high-performance computing platforms for a broad range of applications, their complex memory hierarchies constitute an obstacle for the programmer from a performance point of view. With the goal of making life easier for the application designer, performance optimizations at the machine level for emerging cachecoherent NUMA machines have been explored at Lund University and at University of Southern California. This article exposes the strengths and weaknesses of certain machine-level optimizations based on parallel application case studies and architectural simulations. We focus on what application features they optimize and discuss what implications they have on the machine design as well as what demands they impose on the application software.

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