Formal verification of digital systems (hierarchical modeling, petri nets, verification, rule-based)

A vital need brought on by the continuing VLSI revolution is the development of computer-aided tools which help to ameliorate the difficulties faced by logic designers when they are required to verify properties about their designs. Recently, interest has grown in the possibility of developing alternatives to standard simulation as a means of dealing with this problem. Several researchers suggest that use of artificial intelligence techniques as such an alternative. The purpose of this thesis is to develop a framework under which formal verification tools can be developed and evaluated, and to describe a specific tool that uses an automated reasoning system together with Petri nets for analyzing and modeling digital systems at various levels of abstraction. This thesis expands the previous work in this area along several dimensions: (1) A more generic representation and methodology is established which permits the hierarchical verification of a wider range of properties of digital systems; (2) The employment of a notation that provides coherence between various design verification tools, and models the linkage between software and hardware; and (3) The demonstration of the above with a specific implementation that formally verifies realistic systems by utilizing an interactive theorem prover, ITP, that is based on a reasoning package developed at Argonne National Laboratory called Logic Machine Architecture (LMA). Examples include an ALU based on the 74LS181 to illustrate the verification of logical correctness and the Charles Stark Draper Laboratory Fault-Tolerant Processor to demonstrate how fault-tolerance can be shown.