A Novel Approach to Voltage-Drop Aware Placement in Large SoCs in Advanced Technology Nodes

High supply voltage drops in a circuit may lead to significant performance degradation and even malfunction in lower technology nodes like 45nm and below. Existing placement algorithms do not model voltage drops as an optimization objective and thus causes problems in power-integrity convergence. To remedy this deficiency, we propose a methodology to place the high power consumptions logic in lower IR (voltage) drop regions. We divide the whole floor plan into different buckets after doing an early voltage drop analysis, assuming virtual current sources in every 5u, at the lowest level metal on the PG grid. We propose to plug-in package, PCB parasitic and perform an early static and dynamic IR drop analysis by industry standard tools. The key efforts in this regard were logic clustering and region based placement. The placement regions are planned such that the high frequency logic blocks are placed in low IR drop buckets and low frequency logic blocks are placed in higher voltage drop regions. Our experimental results show 11 % improvement in peak voltage drop and 19% improvement in average voltage drop.