A High-PSR EMI-Resistant NMOS-Only Voltage Reference Using Zero- $V_T$ Active Loads

Electromagnetic interference (EMI) disturbances coupled in the power supply of voltage and current references can severely degrade their performance, due to its finite power supply rejection (PSR). The design of a 90-dB PSR 4-dBm EMI-resistant NMOS-only voltage reference is herein presented. The voltage reference is designed based on the zero-temperature-coefficient transistor operating point. The high PSR is obtained using zero-<inline-formula> <tex-math notation="LaTeX">$V_{T}$</tex-math></inline-formula> transistors as active loads in the open and feedback loop of the circuit. Two versions, using standard <inline-formula><tex-math notation="LaTeX">$V_{T}$</tex-math> </inline-formula> and low-power <inline-formula><tex-math notation="LaTeX">$V_{T}$</tex-math></inline-formula> transistors, were designed in a 130-nm CMOS process. Both are designed using the same thermal compensation principle. The circuits occupy 0.014 and 0.006 mm<inline-formula><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula> of silicon area while consuming around 1.15 and 0.156<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W at 27 <inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula>C, respectively. Postlayout simulations present a reference voltage of 206 and 450 mV with an average temperature coefficient of 321 and 86 ppm/<inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula>C (1000 samples), under a temperature range from <inline-formula><tex-math notation="LaTeX">$-$</tex-math></inline-formula>55 to 125 <inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula>C. An EMI source of 4 dBm (1 <inline-formula><tex-math notation="LaTeX">$\text{V}_{\text{pp}}$</tex-math></inline-formula>) injected in the power supply, according to the direct power injection standard, yields <inline-formula><tex-math notation="LaTeX">$-$ </tex-math></inline-formula>0.17% and <inline-formula><tex-math notation="LaTeX">$-$</tex-math></inline-formula> 0.1<inline-formula><tex-math notation="LaTeX">${\%}$</tex-math></inline-formula> of the maximum dc shift and 822 and 950 <inline-formula><tex-math notation="LaTeX">$\mu \text{V}_{\text{pp}}$</tex-math></inline-formula> of the maximum peak-to-peak ripple for the standard <inline-formula><tex-math notation="LaTeX">$V_{T}$</tex-math></inline-formula> and low-power <inline-formula><tex-math notation="LaTeX">$V_{T}$</tex-math></inline-formula> implementations, respectively.