Lightweight secure PUFs

To ensure security and robustness of the next generation of Physically Unclonable Functions (PUFs), we have developed a new methodology for PUF design. Our approach employs integration of three key principles: (i) inclusion of multiple delay lines for creation of each response bit; (ii) transformations and combination of the challenge bits; and (iii) combination of the outputs from multiple delay lines; to create modular, easy to parameterize, secure and reliable PUF structures. Statistical analysis of the new structure and its comparison with existing PUFs indicates a significantly lower predictability, and higher resilience against circuit faults, reverse engineering and other security attacks.

[1]  Srinivas Devadas,et al.  Silicon physical random functions , 2002, CCS '02.

[2]  Srinivas Devadas,et al.  Identification and authentication of integrated circuits , 2004, Concurr. Pract. Exp..

[3]  Marten van Dijk,et al.  A technique to build a secret key in integrated circuits for identification and authentication applications , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[4]  Srinivas Devadas,et al.  Identification and authentication of integrated circuits: Research Articles , 2004 .

[5]  Martin Feldhofer,et al.  A Case Against Currently Used Hash Functions in RFID Protocols , 2006, OTM Workshops.

[6]  Peter Y. K. Cheung,et al.  Within-die delay variability in 90nm FPGAs and beyond , 2006, 2006 IEEE International Conference on Field Programmable Technology.

[7]  Miodrag Potkonjak,et al.  Remote activation of ICs for piracy prevention and digital right management , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[8]  Leonid Bolotnyy,et al.  Physically Unclonable Function-Based Security and Privacy in RFID Systems , 2007, Fifth Annual IEEE International Conference on Pervasive Computing and Communications (PerCom'07).

[9]  Miodrag Potkonjak,et al.  CAD-based Security, Cryptography, and Digital Rights Management , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[10]  G. Edward Suh,et al.  Physical Unclonable Functions for Device Authentication and Secret Key Generation , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[11]  Farinaz Koushanfar,et al.  Active Hardware Metering for Intellectual Property Protection and Security , 2007, USENIX Security Symposium.

[12]  Jorge Guajardo,et al.  FPGA Intrinsic PUFs and Their Use for IP Protection , 2007, CHES.

[13]  Steven Trimberger.  Trusted Design in FPGAs , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[14]  Miodrag Potkonjak,et al.  Testing Techniques for Hardware Security , 2008, 2008 IEEE International Test Conference.

[15]  Farinaz Koushanfar,et al.  N-variant IC design: Methodology and applications , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[16]  B. Gladman,et al.  Security Engineering: a Guide to Building Dependable Distributed Systems Physical Tamper Resistance 14.1 Introduction , 2022 .