Integrated approach for circuit and fault extraction of VLSI circuits

The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, under development. To be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, bipolar or BiCMOS technologies are handled, both in Manhattan and 45/spl deg/ geometries. For complex circuits, higher level information, obtained in the top-down design flow, is used for fault characterization. A sliding window algorithm previously used for circuit extraction, is extended for fault extraction of non-orthogonal geometries.

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