Contributions to the analysis of deterministic noise on ADPLL jitter performance

In this paper an analytical method is presented for estimating the cycle jitter of ADPLL due to power supply noise with deterministic frequency. It leads to the conclusion that jitter heavily depends on the noise frequency and the smallest cycle jitter appears at only integer multiples of oscillation frequency. It also reveals that the relationship between the bandwidth of ADPLL and the DCOs noise-suppression varies depending on the noise frequency. Our method is utilized to study a CMOS ADPLL designed and simulated in SMIC 0.13 μm standard CMOS process. A comparison between the results obtained by our method and those obtained by Hsim simulation proves the accuracy of the predicted model. The measured RMS jitters caused by the switching noise arising from other digital blocks sharing the same power/ground rails on the testing PCB shows that different switching frequency has totally different effect on ADPLL jitter. It sheds some light on the design of power supply network for ADPLL in the practical application.

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