On the parameterized IP core design of the new cryptographic system

This paper is to investigate how we efficiently realize a real-time encryption and decryption system for data transmission and storage in the applications with different requirements. With the proposed new cryptographic system, we have designed the performance-driven reconfigurable signal encryption/decryption architecture and the corresponding parameterized IP core generator. The performance, hardware cost, and security of signal of the proposed IP core design can be configured by some parameters, including packet size, word-length of input data, and the number of processing elements to meet the requirement of application. This IP core has been qualified under RMM coding guidelines, and certified to reach near 100% code coverage using the provided test-benches. With the specified combinations of parameters, the proposed IP core design possesses the throughput rate ranges between 312.5 Mbps and 1.428 Gbps. Thus this design is useful for the embedded system in multimedia applications.

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