Inserting Data Encoding Techniques into NoC-Based Systems

This work investigates the reduction of power consumption in networks-on-chip through the reduction of transition activity using data coding schemes. Power macromodels for NoC and encoding modules were built, allowing the estimation of the power consumption as a function of the transition activity at each module input. Power macromodels are embedded in a system model and a set of simulations are performed, analyzing the trade-off between the power savings due to coding schemes versus the power consumption overhead due to the encoding and decoding modules

[1]  Mary Jane Irwin,et al.  Some issues in gray code addressing , 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

[2]  Diana Marculescu,et al.  Power and performance evaluation of globally asynchronous locally synchronous processors , 2002, ISCA.

[3]  Dennis Sylvester,et al.  Analytical modeling and characterization of deep-submicrometer interconnect , 2001 .

[4]  Luca Benini,et al.  Architectures and synthesis algorithms for power-efficient businterfaces , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Fernando Gehm Moraes,et al.  HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..

[6]  Massoud Pedram,et al.  Power minimization in IC design: principles and applications , 1996, TODE.

[7]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[8]  Arlindo L. Oliveira,et al.  Low Overhead Encodings For Reduced Activity In Data And Address Buses , 1999 .

[9]  Fernando Gehm Moraes,et al.  Mapping Embedded Systems onto NoCs - The Traffic Effect on Dynamic Energy Estimation , 2005, 2005 18th Symposium on Integrated Circuits and Systems Design.

[10]  PedramMassoud.  Power minimization in IC design , 1996 .

[11]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[12]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Thomas D. Burd,et al.  Energy efficient microprocessor design , 2001 .

[14]  Taewhan Kim,et al.  Bus-invert coding for low-power I/O - a decomposition approach , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[15]  Edward A. Lee,et al.  Heterogeneous Concurrent Modeling and Design in Java (Volume 1: Introduction to Ptolemy II) , 2008 .

[16]  Ney Laert Vilar Calazans,et al.  MAIA - a framework for networks on chip generation and verification , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..