论文信息 - A Low-IF CMOS Simultaneous GPS Receiver Integrated in a Multimode Transceiver

A Low-IF CMOS Simultaneous GPS Receiver Integrated in a Multimode Transceiver

This paper describes a GPS receiver circuit that operates simultaneously with WCDMA/CDMA2000 transceivers. This receiver uses a low-IF architecture to minimize the external passive components. The RF front-end circuit dynamically adjusts the linearity performance based on the instantaneous transmitting power of the integrated transmitter. The receiver measured performances are >80dB gain, 2.0dB noise figure, >20dB image rejection, maximum out-of-band IIP3 is +6dBm. The synthesize features -132dBc/Hz phase noise at 1MHz offset frequency and a total integrated double sideband phase noise of less than -30dBc in the 100Hz to 1MHz band. The receiver is fabricated in a 0.18 mum RFCMOS process, and draws 36.7mA at high linearity mode and 27.4mA at low linearity mode using switch mode power supply.

[1] T. Krishnaswamy,et al. A 90nm CMOS single-chip GPS receiver with 5dBm out-of-band IIP3 2.0dB NF , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[2] Mohammad Nariman,et al. A fully integrated low-IF CMOS GPS radio with on-chip analog image rejection , 2002, IEEE J. Solid State Circuits.

[3] Andrea Baschirotto,et al. A 35-mW 3.6-mm/spl 2/ fully integrated 0.18-μm CMOS GPS radio , 2003 .

[4] M. del Mar Hershenson,et al. A 115-mW, 0.5-/spl mu/m CMOS GPS receiver with wide dynamic-range active filters , 1998 .

[5] Michiel Steyaert,et al. Low-IF topologies for high-performance analog front ends of fully integrated receivers , 1998 .

[6] Hirad Samavati,et al. A 115-mW, 0.5-μm CMOS GPS receiver with wide dynamic-range active filters , 1998, IEEE J. Solid State Circuits.

[7] M. Steyaert,et al. A fully-integrated GPS receiver front-end with 40 mW power consumption , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).