Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings"
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For original paper see J. Yuan and C. Svensson, ibid., vol.32, pp.62-69 (1997). In a recent paper, Yuan and Svensson propose various single-clock differential flip-flops; however, those using a dynamic slave are unsafe in the presence of input glitches. Further, a double-edge triggered flip-flop is developed from one of the semistatic versions.
[1] C. Svensson,et al. New TSPC latches and flipflops minimizing delay and power , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.
[2] G. M. Blair. Comment on new differential flip-flops from Yuan and Svensson , 1996 .