Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders

In this letter, we present a novel methodology to calculate the arithmetic error rate (AER) for deterministic approximate adder architectures, where the calculation of each output bit is restricted to a subset of the input bits, denoted as visibilities. Such architectures have been widely proposed in the literature and are, e.g., obtained when splitting the carry chain in a carry-propagate adder into partitions each computed by a separate parallel adder, or when removing carry-lookahead operators in a parallel prefix adder. Our contribution is a unified calculus for determining the ARE for: 1) such deterministic approximate adder architectures making use of visibilities and 2) the general case of arbitrarily (also nonuniformly) distributed input bits.

[1]  Fabrizio Lombardi,et al.  An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders , 2015, IEEE Transactions on Computers.

[2]  Fabrizio Lombardi,et al.  New Metrics for the Reliability of Approximate and Probabilistic Adders , 2013, IEEE Transactions on Computers.

[3]  Davide De Caro,et al.  Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[5]  Fabrizio Lombardi,et al.  A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits , 2017, ACM J. Emerg. Technol. Comput. Syst..

[6]  Peter J. Varman,et al.  High performance reliable variable latency carry select addition , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[7]  Jürgen Teich,et al.  A LUT-Based Approximate Adder , 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[8]  Jürgen Teich,et al.  FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs , 2016, 2016 International Conference on Field-Programmable Technology (FPT).

[9]  Andrew B. Kahng,et al.  Accuracy-configurable adder for approximate arithmetic designs , 2012, DAC Design Automation Conference 2012.

[10]  Muhammad Shafique,et al.  A low latency generic accuracy configurable adder , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Ronald F. DeMara,et al.  Designing energy-efficient approximate adders using parallel genetic algorithms , 2015, SoutheastCon 2015.

[12]  Gang Wang,et al.  Enhanced low-power high-speed adder for error-tolerant application , 2009, 2010 International SoC Design Conference.

[13]  Mark S. K. Lau,et al.  Modeling of Probabilistic Ripple-Carry Adders , 2010, 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications.

[14]  Alessandro Cilardo.  A new speculative addition architecture suitable for two's complement operations , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[15]  Paolo Ienne,et al.  Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design , 2008, 2008 Design, Automation and Test in Europe.

[16]  Rakesh Kumar,et al.  On reconfiguration-oriented approximate adder design and its application , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).