High performance Si/SiGe pMOSFETs fabricated in a standard CMOS process technology
暂无分享,去创建一个
Nadine Collaert | Roger Loo | K. De Meyer | Matty Caymax | Peter Verheyen | N. Collaert | R. Loo | M. Caymax | P. Verheyen | K. Meyer
[1] J. Hauser,et al. Extraction of experimental mobility data for MOS devices , 1996 .
[2] W. D. Boer,et al. Drift mobilities and Hall scattering factors of holes in ultrathin Si1−xGex layers (0.3 , 2000 .
[3] Evan H. C. Parker,et al. SiGe heterostructures for FET applications , 1998 .
[4] T. Tatsumi,et al. Facet formation mechanism of silicon selective epitaxial layer by Si ultrahigh vacuum chemical vapor deposition , 1994 .
[5] René A. J. Janssen,et al. Electrochemical Society Proceedings , 2000 .
[6] T. Skotnicki,et al. Multiple SiGe well: a new channel architecture for improving both NMOS and PMOS performances , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).
[8] A. Waite,et al. Enhanced Velocity Overshoot and Transconductance in Si/Si(0.64)Ge(0.36)/Si pMOSFETs - Predictions for Deep Submicron Devices , 2001, 31st European Solid-State Device Research Conference.