On the formal verification of a SystemC Packet switch model

In this paper, we present an approach to formally verify SystemC intellectual properties (IPs). We considered as illustrative case a Packet Switch model part of the SystemC library. We propose a verification methodology composed of two steps: (1) static code analysis using abstract interpretation; and (2) model checking. This latter is performed thanks to an integration of both the Property Specification Language (PSL) and the SystemC semantics in the Abstract States Machines (ASMs). We propose a technique based on a reachability algorithm part of the AsmL tool that translates the ASM code combining both the design and the properties into a finite state machine (FSM) representation. We use the generated FSM to run model checking on an external tool, here SMV. Our approach takes advantage from the ASM language capabilities to model designs at the system level as well as from the power of the AsmL tool in generating both a C# code and an FSM representation from an ASMmodel. The experimental results illustrate, in particular, a corner-case bug that we were able to detect in the design under verification.