Impact and compensation of dead time on common mode voltage elimination modulation for neutral-point-clamped three-phase inverters

This paper presents a detailed analysis on the impact of dead time (DT) on the EMI performance of three-level neutral-point-clamping (3L-NPC) inverters with Common Mode Elimination (CME) modulation. The implementation method of CME modulation is presented and the benefits and drawbacks are discussed which shows that the benefit of CME modulation is highly related with the DT added to the system and make it less practical in a real system. By analyzing the switching states of one phase leg, the impacts of DT on CM voltage are discussed in detail. Based on this analysis, a DT compensation method for CME modulations is proposed, where the position of the compensated pulses need to be considered carefully to achieve both CM voltage reduction and the current distortion minimization. Both simulation and experimental verification are implemented to verify the analysis based on a 2.5 kW prototype and the results match well with the analysis and verify the proposed method.

[1]  Fang Zheng Peng,et al.  Multilevel converters-a new breed of power converters , 1995, IAS '95. Conference Record of the 1995 IEEE Industry Applications Conference Thirtieth IAS Annual Meeting.

[2]  A. von Jouanne,et al.  Multilevel inverter modulation schemes to eliminate common-mode voltages , 1998, Conference Record of 1998 IEEE Industry Applications Conference. Thirty-Third IAS Annual Meeting (Cat. No.98CH36242).

[3]  Dushan Boroyevich,et al.  A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters , 2000 .

[4]  Dongsheng Zhou,et al.  Dead-time effect and compensations of three level neutral point clamp inverters for high performance drive applications , 1997, Proceedings of the IECON'97 23rd International Conference on Industrial Electronics, Control, and Instrumentation (Cat. No.97CH36066).

[5]  Hirofumi Akagi,et al.  A New Neutral-Point-Clamped PWM Inverter , 1981, IEEE Transactions on Industry Applications.

[6]  T.A. Lipo,et al.  On-line dead time compensation technique for open-loop PWM-VSI drives , 1998, APEC '98 Thirteenth Annual Applied Power Electronics Conference and Exposition.

[7]  R.M. Cuzner,et al.  Implementation of a Four-Pole Dead-Time-Compensated Neutral-Point-Clamped Three-Phase Inverter With Low Common-Mode Voltage Output , 2009, IEEE Transactions on Industry Applications.

[8]  Rae-Young Kim,et al.  A novel SVPWM strategy considering DC-link balancing for a multi-level voltage source inverter , 1999, APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285).

[9]  Satoru Sone,et al.  Switching loss minimised space vector PWM method for IGBT three-level inverter , 1997 .

[10]  T. Lipo,et al.  Elimination of common mode voltage in three phase sinusoidal power converters , 1996, PESC Record. 27th Annual IEEE Power Electronics Specialists Conference.

[11]  Dushan Boroyevich,et al.  A fast space vector modulation algorithm for multilevel three-phase converters , 1999, Conference Record of the 1999 IEEE Industry Applications Conference. Thirty-Forth IAS Annual Meeting (Cat. No.99CH36370).

[12]  Leon M. Tolbert,et al.  Multilevel converters for large electric drives , 1999 .