Evaluation of function blocks for asynchronous design

We analyze implementation techniques for boolean functions for speed independent circuitry, that is, asynchronous circuitry where the functionality is unaffected by any delays in circuit elements. We compare the implementation techniques with respect to their general characteristics such as delay assumptions, ease of synthesis, area complexity, and computation delay. The area and delay are quantified through implementations of a common example. In general, speed independent function blocks have a significant area overhead compared to standard combinational logic, whereas the delays are approximately the same.