论文信息 - C-10-4 InP HBT 50-Gbit/s 1 : 4 Demultiplexer IC with Multiphase Clock Architecture - 字舞流文

C-10-4 InP HBT 50-Gbit/s 1 : 4 Demultiplexer IC with Multiphase Clock Architecture

Kimikazu Sano | Michihiro Hirata | Koichi Murata | Shoji Yamahata | Takatomo Enoki | Kenji Kurishima | Minoru Ida | Hirohiko Sugahara