An ultra-low voltage comparator with improved comparison time and reduced offset voltage

This paper presents the design of a modified StrongArm regenerative comparator in 0.13-μm CMOS technology, operating at a supply voltage of 200-mV. The comparator uses a pair of cross-coupled P-type transistors to replace the conventional cross-coupled inverters, improving the comparison time and voltage headroom. A robust S-R latch is proposed to solve the race condition which occurs when the S-R latch enters a forbidden state especially during ultra-low supply voltage operation. As a result, the circuit shows up to 1.8× voltage offset reduction and 73% less sensitivity in the delay per input voltage difference (delay/log(ΔVIN)), which is about 65ns/decade, compared to conventional latched comparators.

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