Hierarchical placement for macrocells: a 'meet in the middle' approach

Placement and related aspects of the BEAR macrocell layout system are described. A combination of top-down and bottom-up heuristics is used to make best use of a hierarchical description. The interdependency of placement and routing is considered explicitly. Experimental results show a considerable improvement over previous approaches.<<ETX>>

[1]  A. Sangiovanni-Vincentelli,et al.  The TimberWolf placement and routing package , 1985, IEEE Journal of Solid-State Circuits.

[2]  Ikuo Harada,et al.  CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Ernest S. Kuh,et al.  A Dynamic and Efficient Representation of Building-Block Layout , 1987, 24th ACM/IEEE Design Automation Conference.

[4]  Fadi J. Kurdahi,et al.  PLEST: A Program for Area Estimation of VLSI Integrated Circuits , 1986, DAC 1986.

[5]  Antoni A. Szepieniec.  Integrated Placement/Routing in Sliced Layouts , 1986, DAC 1986.

[6]  R. Dutton,et al.  An Analytical Algorithm for Placement of Arbitrarily Sized Rectangular Blocks , 1985, DAC 1985.

[7]  Alberto L. Sangiovanni-Vincentelli,et al.  A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Ernest S. Kuh,et al.  Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  William R. Heller,et al.  Prediction of wiring space requirements for LSI , 1977, DAC '77.