A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

[1]  Jehoshua Bruck,et al.  Performance Optimization of Checkpointing Schemes with Task Duplication , 1997, IEEE Trans. Computers.

[2]  Yohei Nakata,et al.  A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM , 2014, ARCS Workshops.

[3]  Earl E. Swartzlander,et al.  Quadruple Time Redundancy Adders , 2003 .

[4]  Yuki Kagiyama,et al.  Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[5]  Jinjun Chen,et al.  A minimum proportional time redundancy based checkpoint selection strategy for dynamic verification of fixed-time constraints in grid workflow systems , 2005, 12th Asia-Pacific Software Engineering Conference (APSEC'05).

[6]  Babak Falsafi,et al.  Reunion: Complexity-Effective Multicore Redundancy , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[7]  Shunsuke Okumura,et al.  7T SRAM enabling low-energy simultaneous block copy , 2010, IEEE Custom Integrated Circuits Conference 2010.

[8]  Takeshi Kataoka,et al.  A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery , 2007, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07).

[9]  Shunsuke Okumura,et al.  A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection , 2009, 2009 22nd International Conference on VLSI Design.

[10]  J. Teifel,et al.  Self-Voting Dual-Modular-Redundancy Circuits for Single-Event-Transient Mitigation , 2008, IEEE Transactions on Nuclear Science.

[11]  J.-M. Yang,et al.  A checkpoint scheme with task duplication considering transient and permanent faults , 2010, 2010 IEEE International Conference on Industrial Engineering and Engineering Management.