The Observation of Width Quantization Impact on Device Performance and Reliability for High-k/Metal Tri-Gate FinFET

In this paper, the impact of width quantization on device characteristic and stressing induced device degradation for high-k/metal tri-gate n/p-type FinFET was investigated well including electrical characteristic clarification and simulation. Carrier conduction in the trapezoidal shape Si-fin body of FinFETs is different for devices with different Fin bottom widths (WFin_bottom), which will impact the device performance and reliability. For n-type FinFETs, the experimental results show that the thinner WFin_bottom device performs better reliability under HCI stress due to higher inversion carrier density at the center of Si-fin channel. For p-type FinFETs under negative bias stressing, the thinner WFin_bottom device shows more serious degradation on drain current (ID) and subthreshold swing (SS) with the increasing of stressing voltage due to larger electric field within the Si-fin and higher energy of inversion holes, while the thicker WFin_bottom device shows almost insensitively degradation with the variation of stressing voltage.

[1]  Paolo Magnone,et al.  Implications of fin width scaling on variability and reliability of high-k metal gate FinFETs , 2010 .

[2]  Donggun Park,et al.  A study of negative-bias temperature instability of SOI and body-tied FinFETs , 2005, IEEE Electron Device Letters.

[3]  Jie Gu,et al.  Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Ching-Te Chuang,et al.  Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits , 2012, IEEE Transactions on Electron Devices.

[5]  Wen-Shiang Liao,et al.  Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs , 2013, IEEE Transactions on Electron Devices.

[6]  C. Merckling,et al.  An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[7]  J. Kavalieros,et al.  High performance fully-depleted tri-gate CMOS transistors , 2003, IEEE Electron Device Letters.

[8]  Ran Yan,et al.  NBTI and hot-carrier effects in accumulation-mode Pi-gate pMOSFETs , 2009, Microelectron. Reliab..

[9]  Andrew R. Brown,et al.  Statistical variability and reliability in nanoscale FinFETs , 2011, 2011 International Electron Devices Meeting.

[10]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[12]  Nuo Xu,et al.  MuGFET carrier mobility and velocity: Impacts of fin aspect ratio, orientation and stress , 2010, 2010 International Electron Devices Meeting.

[13]  T. Lee,et al.  Demonstration of scaled Ge p-channel FinFETs integrated on Si , 2012, 2012 International Electron Devices Meeting.

[14]  A. Boudou,et al.  Interface state creation and charge trapping in the medium-to-high gate voltage range (V/sub d//2>or=V/sub g/, 1990 .

[15]  Daewon Ha.  Molybdenum-Gate HfOz CMOS FinFET Technology , 2005 .

[16]  J. Faricelli,et al.  Examination of the time power law dependencies in hot carrier stressing of n-MOS transistors , 1997, IEEE Electron Device Letters.

[17]  Asen Asenov,et al.  Comparative Simulation Analysis of Process-Induced Variability in Nanoscale SOI and Bulk Trigate FinFETs , 2013, IEEE Transactions on Electron Devices.

[18]  T. Liu,et al.  Impact of Gate-Induced Strain on MuGFET Reliability , 2008, IEEE Electron Device Letters.

[19]  Yoon-Ha Jeong,et al.  Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis , 2013, IEEE Transactions on Electron Devices.

[20]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[21]  E.J. Nowak,et al.  Turning silicon on its edge [double gate CMOS/FinFET technology] , 2004, IEEE Circuits and Devices Magazine.

[22]  G. Dorda,et al.  Positive and negative charge generation by hot carriers in n-MOSFETs , 1983 .

[23]  Jin-Woo Han,et al.  Body Thickness Dependence of Impact Ionization in a Multiple-Gate FinFET , 2007, IEEE Electron Device Letters.

[24]  Gerard Ghibaudo,et al.  Analytical unified threshold voltage model of short-channel FinFETs and implementation , 2011 .

[25]  V. Kilchytska,et al.  Improvement of high-frequency FinFET performance by fin width engineering , 2012, 2012 IEEE International SOI Conference (SOI).

[26]  Byoung Hun Lee,et al.  Process-Dependent N/PBTI Characteristics of TiN Gate FinFETs , 2012, IEEE Electron Device Letters.

[27]  J. Bokor,et al.  Reliability study of CMOS FinFETs , 2003, IEEE International Electron Devices Meeting 2003.

[28]  Donggun Park,et al.  Characteristics of body-tied triple-gate pMOSFETs , 2004, IEEE Electron Device Letters.

[29]  Tomislav Suligoj,et al.  Improving bulk FinFET DC performance in comparison to SOI FinFET , 2009 .

[30]  S. H. Rasouli,et al.  Design Optimization of FinFET Domino Logic Considering the Width Quantization Property , 2010, IEEE Transactions on Electron Devices.

[31]  N. Collaert,et al.  Analysis of the parasitic S/D resistance in multiple-gate FETs , 2005, IEEE Transactions on Electron Devices.

[32]  Wen-Shiang Liao,et al.  Investigation of Reliability Characteristics in NMOS and PMOS FinFETs , 2008, IEEE Electron Device Letters.