A parallel pipelined approach to vedic multiplier for FPGA implementation

As Technology progresses, the speed of a digital system is of prime importance. Most complex system use multipliers, and most often than not it is these multipliers which limit the speed of the system. Many high speed multipliers have been proposed in the past. Multipliers based on Vedic mathematics being one of them. Vedic multiplication algorithm is found to be fast as compared to other multiplication algorithms like Booth or Wallace. However the Vedic multiplier suffers from propagation delay for longer input lengths. A novel pipelined approach, consisting of seven stages is proposed here, so as to reduce the propagation delay. An 8*11 bit pipelined Vedic multiplier to be used for DCT applications is proposed and implemented. It is found to have a maximum clock speed of 179.69 MHz, and an area consisting of 225 slices.