Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study

A decision feedback equalizer (DFE), well suited for implementation in standard CMOS and capable of recovering data sent over a multi-drop memory bus at several Gb/s per wire, is presented. The structure features low latency and permits easy switching of filter coefficient sets, which enables the bus host to receive data from different slaves. Results from near-hardware simulations of 3 Gb/s per wire transmissions over a four tap standard DDR memory bus are presented.

[1]  P.J. Hurst,et al.  A mixed-signal RAM decision-feedback equalizer for disk drives , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[2]  Paul J. Hurst,et al.  Analog decision-feedback equalizer architectures , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

[3]  Bang-Sup Song,et al.  NRZ timing recovery technique for band limited channels , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[4]  R. Mooney,et al.  An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[5]  Vladimir Stojanovic,et al.  Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell , 2003 .