Clocking circuits for a 16Gb/s memory interface

8 GHz clocking circuits for a 16 Gb/s/pin asymmetric memory interface [1] are described. A combination of an LC-PLL and a ring-PLL achieves improved jitter performance for multiple phase outputs with a wide frequency range. A direct phase mixer and a digitally controlled duty-cycle corrector (DCC) are time-multiplexed between transmitter (TX) and receiver (RX), thereby reducing area and power. The prototype chip implemented in a 65 nm CMOS technology has measured 734 fs RJ (rms) at the TX output when operating at 16 Gb/s.

[1]  B. Razavi,et al.  A CMOS interface circuit for detection of 1.2 Gb/s RZ data , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[2]  Ting Wu,et al.  A 16Gb/s/link, 64GB/s bidirectional asymmetric memory interface cell , 2008, 2008 IEEE Symposium on VLSI Circuits.

[3]  J. Wei,et al.  A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[4]  E. Alon,et al.  Replica compensated linear regulators for supply-regulated phase-locked loops , 2006, IEEE Journal of Solid-State Circuits.

[5]  C. Menolfi,et al.  A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  H. Peter Hofstee,et al.  The design methodology and implementation of a first-generation CELL processor: a multi-core SoC , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[7]  D. Friedman,et al.  A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.