Timing-driven global routing with efficient buffer insertion

Timing optimization is an important goal of global routing in the deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becomes inadequate. We present an efficient timing-driven global routing algorithm with buffer insertion. Our approach is capable of applying topological-based timing optimization and buffer insertion simultaneously with routability considerations. Compared with previous work, we efficiently solve the timing issues under a limited buffer usage. Experimental results have demonstrated significant delay improvement within a short runtime with a very small number of buffers inserted.

[1]  Martin D. F. Wong,et al.  Simultaneous routing and buffer insertion with restrictions on buffer locations , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[2]  Andrew B. Kahng,et al.  Hierarchical whitespace allocation in top-down placement , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Yici Cai,et al.  An efficient hierarchical timing-driven Steiner tree algorithm for global routing , 2003, Integr..

[4]  Chris Chu,et al.  An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations , 2004 .

[5]  Xianlong Hong,et al.  TIGER: an efficient timing-driven global router for gate array and standard cell layout design , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[7]  Igor L. Markov,et al.  On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis , 2003, ICCAD 2003.

[8]  L.P.P.P. van Ginneken,et al.  Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990, IEEE International Symposium on Circuits and Systems.

[9]  T. Sakurai,et al.  Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.

[10]  Charles J. Alpert,et al.  Wire segmenting for improved buffer insertion , 1997, DAC.

[11]  D. R. Fulkerson,et al.  Flows in Networks. , 1964 .

[12]  Jason Cong,et al.  Buffered Steiner tree construction with wire sizing for interconnect layout optimization , 1996, ICCAD 1996.

[13]  Sachin S. Sapatnekar,et al.  A timing-constrained algorithm for simultaneous global routing of multiple nets , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[14]  Jun Gu,et al.  UTACO: a unified timing and congestion optimization algorithm for standard cell global routing , 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Chung-Kuan Cheng,et al.  Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1996 .

[16]  Charles J. Alpert,et al.  Buffer insertion for noise and delay optimization , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Chris Chu,et al.  A new approach to simultaneous buffer insertion and wire sizing , 1997, ICCAD 1997.

[18]  Martin D. F. Wong,et al.  Maze routing with buffer insertion and wiresizing , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Yici Cai,et al.  A novel and efficient timing-driven global router for standard cell layout design based on critical network concept , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).