Variability in 3-D integrated circuits

In recent years, there has been a trend among digital and analog circuit designers towards three-dimensional integration. There has been some debate regarding the applicability of 3-D technology to general logic circuits, especially with regard to thermal issues. We examine process variations on the same layer, across layers, and cross-chip variations. We show how the performance of each layer of the 3-D chip varies with temperature, and demonstrate the effect of heat pipes on circuit performance.

[1]  Gabriel H. Loh,et al.  Thermal analysis of a 3D die-stacked high-performance microprocessor , 2006, GLSVLSI '06.

[2]  R. Berger,et al.  Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[3]  R. Ho,et al.  Proximity communication , 2004, IEEE Journal of Solid-State Circuits.

[4]  Sherief Reda,et al.  Strategies for improving the parametric yield and profits of 3D ICs , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[5]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[6]  R. Reif,et al.  Thermal analysis of three-dimensional (3-D) integrated circuits (ICs) , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[7]  K.C. Saraswat,et al.  Thermal analysis of heterogeneous 3D ICs with various integration scenarios , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[8]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[9]  Alain J. Martin.  The limitations to delay-insensitivity in asynchronous circuits , 1990 .

[10]  Krisztián Flautner,et al.  PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor , 2006, ASPLOS XII.

[11]  R. M. Lea,et al.  A 3-D stacked chip packaging solution for miniaturized massively parallel processing , 1999 .

[12]  Yan Zhang,et al.  Thermal-driven multilevel routing for 3D ICs , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[13]  Rajit Manohar,et al.  A Three-Tier Asynchronous FPGA , 2006 .

[14]  Nisha Checka,et al.  Technology, performance, and computer-aided design of three-dimensional integrated circuits , 2004, ISPD '04.

[15]  S. K. Kim,et al.  Three-dimensional integration: technology, use, and issues for mixed-signal applications , 2003 .

[16]  Anantha Chandrakasan,et al.  Timing, energy, and thermal performance of three-dimensional integrated circuits , 2004, GLSVLSI '04.

[17]  Sachin S. Sapatnekar,et al.  Thermal via placement in 3D ICs , 2005, ISPD '05.

[18]  Arifur Rahman,et al.  System-level performance evaluation of three-dimensional integrated circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..