A 1.76-GHz 22.6-mW /spl Delta//spl Sigma/ fractional-n frequency synthesizer

A /spl Delta//spl Sigma/ fractional-N frequency synthesizer for the 2-GHz-range wireless communication applications is implemented in a 0.35-/spl mu/m BiCMOS process, using only CMOS components. The synthesizer achieves a close-in phase noise of -81 dBc/Hz, while the spurious tones are at -85 dBc. The synthesizer features a multiple-modulus prescaler employing the phase-switching architecture to minimize the power dissipation. The entire prescaler, including the gigahertz-speed first stages, is implemented using full-swing logic. The current source structure employed in the charge pump provides a constant output current over a wide, almost rail-to-rail output voltage range. The power dissipation of the synthesizer chip is 22.6 mW from a 2.7-V supply.

[1]  N. Tracht,et al.  A sub-1 mA 1.5 GHz silicon bipolar dual modulus prescaler , 1993, 1993 Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

[2]  T. Riley,et al.  Delta-sigma modulation in fractional-N frequency synthesis , 1993 .

[3]  Jan Craninckx,et al.  A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-/spl mu/m CMOS , 1996 .

[4]  K. Halonen,et al.  A 4 GHz CMOS multiple modulus prescaler , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[5]  Michael H. Perrott,et al.  A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation , 1997, IEEE J. Solid State Circuits.

[6]  K. Halonen,et al.  A novel phase detector with no dead zone and a chargepump with very wide output voltage range , 1998, Proceedings of the 24th European Solid-State Circuits Conference.

[7]  Behzad Razavi,et al.  Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS , 1995, IEEE J. Solid State Circuits.