Adapting scan architectures for low power operation

Scan architectures are commonly used to test digital circuitry in integrated circuits. This paper describes a method of adapting conventional scan architectures such that they operate in a low power mode during test. The adapted scan architectures maintain the test times of the pre-adapted scan architectures. Also, the adaptation occurs in a manner that enables the test patterns of the pre-adapted scan architecture to be directly reusable in the adapted scan architecture.

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