Approximate compressor based multiplier design methodology for error-resilient digital signal processing

Multiplier is a fundamental component for digital signal processing (DSP) applications and takes up the most part of the resource utilization, namely power and area. Approximate circuitry architectures have been studied as innovative paradigm for reducing resource utilization for DSP systems. In this paper, the 4:2 compressor based approximate multiplier architecture which uses both truncation and approximation of compressor is studied. A greedy selection algorithm is then proposed to identify the Pareto frontier to give the optimal accuracy-power tradeoff. A finite impulse response (FIR) filter is used as an assessment. The architecture proposed in this paper has achieved up to 21.03% and 27.72% saving on power and area for FIR filter case compared to conventional multiplier designs with a decrease of 0.3dB in output SNR.

[1]  Thomas A. DeMassa,et al.  Digital Integrated Circuits , 1985, 1985 IEEE GaAs IC Symposium Technical Digest.

[2]  Kevin J. Nowka,et al.  A 16-bit/spl times/16-bit MAC design using fast 5:2 compressors , 2000, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors.

[3]  Earl E. Swartzlander,et al.  Analysis of column compression multipliers , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[4]  Naveen Kr. Gahlan.  Implementation of Wallace Tree Multiplier Using Compressor , 2012 .

[5]  Bruce A. Wooley,et al.  A Two's Complement Parallel Array Multiplication Algorithm , 1973, IEEE Transactions on Computers.

[6]  Chip-Hong Chang,et al.  Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[7]  Fabrizio Lombardi,et al.  Approximate compressors for error-resilient multiplier design , 2015, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

[8]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[9]  K.K. Parhi,et al.  Low-power 4-2 and 5-2 compressors , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[10]  Shuguo Li,et al.  A new high compression compressor for large multiplier , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[11]  Jie Han,et al.  Approximate computing: An emerging paradigm for energy-efficient design , 2013, 2013 18th IEEE European Test Symposium (ETS).

[12]  Ing-Chao Lin,et al.  High accuracy approximate multiplier with error correction , 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

[13]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[14]  Fabrizio Lombardi,et al.  New Metrics for the Reliability of Approximate and Probabilistic Adders , 2013, IEEE Transactions on Computers.

[15]  Sung-Mo Kang,et al.  CMOS digital integrated circuits , 1995 .

[16]  Earl E. Swartzlander,et al.  16-bit × 16-bit MAC design using fast 5:2 compressors , 2000 .