An Efficient Switch Design for Scheduling Real-Time Multicast Traffic

In this paper we put forth a switch design in terms of architecture and service discipline for real-time multicast traffic in packet switching networks. A parallel switching architecture called POQ (parallel output-queued) is employed, which take the advantages of both OQ (output-queued) and IQ (input-queued) switch architectures, i.e., non-blocking and low speedup of switch buffer. Basing on the POQ architecture we propose a hierarchical service discipline called H-EDF-RR (hierarchical earliest-deadline-first round-robin), which intends to simultaneously schedule both unicast and multicast traffic composed of fixed-length cells with guaranteed performances. Analyses show that this design can provide tight delay bounds and buffer requirements, and has computational complexity of O(1). These properties make the proposed switch design well suitable in real-time distributed systems.

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