Analog design optimization using symbolic approach

The authors present a technique for circuit structure optimization which can be used in an analog design process. The symbolic simulator used in this process can greatly enhance the performance of the proposed method. An organizational structure is proposed to implement a design strategy to solve specific design problems. The method is a heuristic one and in general provides satisfactory solutions when a class of topologies is constrained. An example is presented in order to show how the proposed technique permits minimization of the cost function while fulfilling the circuit specifications in the class of accepted topologies.<<ETX>>