On the reconfiguration of degradable VLSI/WSI arrays

This paper consider the problem of reconfiguring two dimensional very large scale integration (VLSI/WSI) arrays via the degradation approach. In this approach, all elements are treated uniformly and no elements are dedicated as spares. The goal is to derive a fault-free subarray T from the defective host array such that the dimensions of T are larger than some specified minimum. This problem has been shown to be NP-complete under various switching and routing constraints. However, we show that a special case of the reconfiguration problem with row bypass and column rerouting capabilities is optimally solvable in linear time. Using this result, a new fast and efficient reconfiguration algorithm is proposed. Empirical study shows that the new algorithm indeed produces good results in terms of the percentages of harvest and degradation of VLSI/WSI arrays.

[1]  Israel Koren,et al.  Fault spectrum analysis for fast spare allocation in reconfigurable arrays , 1992, Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[2]  Anton T. Dahbura,et al.  Increased Thoughput for the Testing and Repair of RAM's with Redundancy , 1991, IEEE Trans. Computers.

[3]  Mariagiovanna Sami,et al.  Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays , 1989 .

[4]  L. LaForge,et al.  Extremally fault tolerant arrays , 1989, [1989] Proceedings International Conference on Wafer Scale Integration.

[5]  Nany Hasan,et al.  Minimum fault coverage in reconfigurable arrays , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[6]  T.E. Mangir.  Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part II—Restructurable interconnects for RVLSI and WSI , 1984, Proceedings of the IEEE.

[7]  John Day.  A Fault-Driven, Comprehensive Redundancy Algorithm , 1985, IEEE Design & Test of Computers.

[8]  Fabrizio Lombardi,et al.  Approaches for the repair of VLSI/WSI RRAMs by row/column deletion , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[9]  H. W. Leong,et al.  On the configuration of degradable VLSI/WSI arrays , 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[10]  Edwin H. Rogers,et al.  Architectural yield analysis of random defects in wafer scale integration , 1989, [1989] Proceedings International Conference on Wafer Scale Integration.

[11]  Sy-Yen Kuo,et al.  Efficient reconfiguration algorithms for degradable VLSI/WSI arrays , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Chin-Long Wey,et al.  On the Repair of Redundant RAM's , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Sun-Yuan Kung,et al.  Fault-Tolerant Array Processors Using Single-Track Switches , 1989, IEEE Trans. Computers.

[14]  James A. McHugh,et al.  Algorithmic Graph Theory , 1986 .

[15]  Sudhakar M. Reddy,et al.  On the Repair of Redundant RAMs , 1989, 26th ACM/IEEE Design Automation Conference.

[16]  Frank Thomson Leighton,et al.  Wafer-Scale Integration of Systolic Arrays , 1985, IEEE Trans. Computers.

[17]  W. Kent Fuchs,et al.  Efficient Spare Allocation for Reconfigurable Arrays , 1987 .

[18]  C.L. Liu,et al.  Fast search algorithms for reconfiguration problems , 1991, [Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems.

[19]  W. Kent Fuchs,et al.  Diagnosis and Repair of Large Memories: A Critical Review and Recent Results , 1989 .