CAD for low power: status and promising directions

Low power design is gaining increasing attention as the market for battery powered portable products expands and as power consumption becomes the stumbling block for further system integration. This paper examines strategies to minimize power consumption of digital circuits by reducing the supply voltage, by using power-conscious design methodologies and tools at the behavioral, logic and circuit levels, and by dynamic power management. The paper highlights some of the more effective and promising approaches for achieving ultra low power VLSI circuits and systems.

[1]  Joe G. Xi,et al.  Low Power Clock Distribution , 1996 .

[2]  Massoud Pedram,et al.  PCUBE: A performance driven placement algorithm for low power designs , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[3]  Farid N. Najm,et al.  Towards a high-level power estimation capability , 1995, ISLPED '95.

[4]  Mary Jane Irwin,et al.  Power-delay characteristics of CMOS adders , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Kurt Keutzer,et al.  On average power dissipation and random pattern testability of CMOS combinational logic networks , 1992, ICCAD.

[6]  Ibrahim N. Hajj,et al.  Probabilistic simulation for reliability analysis of CMOS VLSI circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Radu Marculescu,et al.  Efficient Power Estimation for Highly Correlated Input Streams , 1995, 32nd Design Automation Conference.

[8]  Edward J. McCluskey,et al.  Probabilistic Treatment of General Combinational Networks , 1975, IEEE Transactions on Computers.

[9]  Alex Orailoglu,et al.  Microarchitectural synthesis of performance-constrained, low-power VLSI designs , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[10]  Jan M. Rabaey,et al.  Power estimation for high level synthesis , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[11]  Massoud Pedram,et al.  Power conscious CAD tools and methodologies: a perspective , 1995, Proc. IEEE.

[12]  Kurt Keutzer,et al.  Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Luca Benini,et al.  Transformation and synthesis of FSMs for low-power gated-clock implementation , 1995, ISLPED '95.

[14]  Chi-Ying Tsui,et al.  Low Power Architectural Design and Compilation Techniques for High-Performance Processor , 1994 .

[15]  Niraj K. Jha,et al.  Behavioral synthesis for low power , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[16]  Marios C. Papaefthymiou,et al.  Precomputation-based sequential logic optimization for low power , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[17]  Chi-Ying Tsui,et al.  Power Estimation Considering Charging and Discharging of Internal Nodes of CMOS Gates , 1993 .

[18]  Sharad Malik,et al.  Technology Mapping for Low Power , 1993, 30th ACM/IEEE Design Automation Conference.

[19]  Ping Yang,et al.  A Monte Carlo approach for power estimation , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[20]  Massoud Pedram,et al.  Efficient estimation of dynamic power consumption under a real delay model , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[21]  Nestoras Tzartzanis,et al.  Low-power digital systems based on adiabatic-switching principles , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[22]  Miodrag Potkonjak,et al.  HYPER-LP: a system for power minimization using architectural transformations , 1992, ICCAD 1992.

[23]  A. Despain,et al.  Low Power State Assignment Targeting Two- And Multi-level Logic Implementations , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[24]  R.W. Brodersen,et al.  A portable multimedia terminal , 1992, IEEE Communications Magazine.

[25]  Anantha P. Chandrakasan,et al.  Design of portable systems , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[26]  Kaushik Roy,et al.  Circuit activity based logic synthesis for low power reliable operations , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[27]  Jason Cong,et al.  Simultaneous Driver And Wire Sizing For Performance And Power Optimization* , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[28]  Massimo Poncino,et al.  Re-encoding sequential circuits to reduce power dissipation , 1994, ICCAD '94.

[29]  L. S. Nielsen,et al.  Low-power operation using self-timed circuits and adaptive scaling of the supply voltage , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[30]  Chi-Ying Tsui,et al.  Power efficient technology decomposition and mapping under an extended power consumption model , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  Chi-Ying Tsui,et al.  Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs , 1994, 31st Design Automation Conference.

[32]  Hugo De Man,et al.  Low-power driven technology mapping under timing constraints , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[33]  Sharad Malik,et al.  Power analysis of embedded software: a first step towards software power minimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[34]  Hugo De Man,et al.  Global Communication and Memory Optimizing Transformations for Low Power Systems , 1994 .

[35]  Miodrag Potkonjak,et al.  HYPER-LP: a system for power minimization using architectural transformations , 1992, ICCAD.

[36]  Massoud Pedram,et al.  Multi-level Network Optimization For Low Power , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[37]  Radu Marculescu,et al.  Information theoretic measures of energy consumption at register transfer level , 1995, ISLPED '95.

[38]  Srinivas Devadas,et al.  Retiming sequential circuits for low power , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).