A parallel hierarchical design rule checker

The halo algorithm, a novel and efficient algorithm for hierarchical design-rule checking (DRC) has been modified for parallel processing. Like the sequential halo algorithm, the parallel version identifies repeated subcell interactions and checks them only once thereby improving performance substantially. Inverse layout trees are used to handle interacting primitives hierarchically. The algorithm has been implemented on workstations connected by a local area network and on a shared memory multicomputer.<<ETX>>

[1]  John K. Ousterhout,et al.  Lyra: A New Approach to Geometric Layout Rule Checking , 1982, DAC 1982.

[2]  Randy Lee Brown Multiple Storage Quad Trees: A Simpler Faster Alternative to Bisector List Quad Trees , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Kjell O. Jeppson,et al.  The use of inverse layout trees for hierarchical design verification , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[4]  Prithviraj Banerjee,et al.  PACE: a parallel VLSI extractor on the Intel hypercube multiprocessor , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[5]  Prithviraj Banerjee,et al.  A parallel algorithm for hierarchical circuit extraction , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[6]  Andrew R. Pleszkun,et al.  An Algorithm for Design Rule Checking on a Multiprocessor , 1985, DAC 1985.

[7]  Sartaj Sahni,et al.  A Systolic Design-Rule Checker , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Rob A. Rutenbar,et al.  Mask verification on the Connection Machine , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[9]  Prithviraj Banerjee,et al.  PACE2: an improved parallel VLSI extractor with parameter extraction , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[10]  Kjell O. Jeppson,et al.  The Use of Inverse Layout Trees for Hierarchical Design Rule Checking , 1989, 26th ACM/IEEE Design Automation Conference.

[11]  Rod D. W. Widdowson,et al.  Parallel polygon operations using loosely coupled workstations , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.