论文信息 - 65nm Low Power (LP) SOI Technology on High Resistivity (HR) Substrate for WLAN and Mmwave SOCs - 字舞流文

65nm Low Power (LP) SOI Technology on High Resistivity (HR) Substrate for WLAN and Mmwave SOCs

Baudouin Martineau | Frederic Gianesello | Georges Guegan | Sebastien Haendler | Nicolas Planes | Christine Raynaud | P. Touret