论文信息 - A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC

A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC

This brief introduces a voltage-current-time (V-I-T) 3-domain 3-stage pipelined analog-to-digital converter (ADC) that exploits both the current-domain and the time-domain residue processing for speed enhancement. An open-loop current-time (I-T) pipeline with a calibration-free time-to-digital converter (TDC) utilizing a full-scale-matched current-to-time converter (ITC) enhances the conversion speed of a time-domain backend ADC while ensuring robustness to process, voltage, and temperature (PVT) variation. With background calibrations of voltage-to-current residue gain and sampling time skew at the first stage, the prototype 12-bit 250-MS/s ADC fabricated in a 28-nm CMOS process achieves a signal-to-noise-and-distortion ratio (SNDR) of 61.5 dB at a Nyquist input, resulting in a 22.2-fJ/conversion-step Walden figure-of-merit (FoM) under a 1.0V supply.

Seung-Tak Ryu | Kyoung-Jun Moon | Dong-Ryeol Oh | Michael Choi

[1] Seung-Tak Ryu,et al. A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS , 2019, IEEE Journal of Solid-State Circuits.

[2] Un-Ku Moon,et al. A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information , 2014, IEEE Journal of Solid-State Circuits.

[3] Yang Xu,et al. A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization , 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

[4] Gin-Kou Ma,et al. SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration , 2011, IEEE Journal of Solid-State Circuits.

[5] Tao Wang,et al. A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.

[6] Fa Foster Dai,et al. A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS , 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

[7] Rui P. Martins,et al. A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques , 2019, IEEE Journal of Solid-State Circuits.

[8] Chih-Cheng Hsieh,et al. A 2.02–5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS , 2016, IEEE Journal of Solid-State Circuits.

[9] Wan Kim,et al. A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC , 2016, IEEE Journal of Solid-State Circuits.