Domino-Logic-Based ADC for Digital Synthesis

A low-power synthesizable analog-to-digital converter (ADC) is presented. By cascading many digital-like domino-logic cells whose propagation delay is influenced by an analog input voltage, a digital value is obtained at the end of the allowed ripple period by determining the number of cells that the ripple passed through. The sample-and-hold is simply a bootstrapped switch into a small sampling capacitor. As each domino-logic cell passes the ripple, charge is kicked back onto the input capacitor, which creates a significant second harmonic. Distortion caused by even harmonics is canceled by implementing a pseudodifferential structure. A test chip is fabricated in 0.18-μm CMOS. The test chip achieves over 5.4-bit effective number of bits up to 50 MS/s with a 1.3-V supply. With a sampling frequency of 50 MS/s and a 24-MHz input, a 34.2-dB signal-to-noise-plus distortion ratio is achieved while consuming 433 μW and occupying only 0.094 mm2.

[1]  Michael P. Flynn,et al.  A "digital" 6-bit ADC in 0.25-μm CMOS , 2002 .

[2]  E. Sail,et al.  A multiplexer based decoder for flash analog-to-digital converters , 2004, 2004 IEEE Region 10 Conference TENCON 2004..

[3]  Manoj Sachdev,et al.  A fully digital ADC using a new delay element with enhanced linearity , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[4]  Y. Makino,et al.  An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering , 2003, IEEE J. Solid State Circuits.

[5]  Denis C. Daly,et al.  A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[6]  Andreas Kaiser,et al.  A 1 V 1 mW digital-audio /spl Delta//spl Sigma/ modulator with 88 dB dynamic range using local switch bootstrapping , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[7]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[8]  B. Nauta,et al.  Analog circuits in ultra-deep-submicron CMOS , 2005, IEEE Journal of Solid-State Circuits.

[9]  Hiroshi Iwai.  CMOS scaling towards its limits , 1998, 1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105).

[10]  Mohamed Dessouky,et al.  Very low-voltage digital-audio /spl Delta//spl Sigma/ modulator with 88-dB dynamic range using local switch bootstrapping , 2001 .

[11]  Andreas Kaiser,et al.  Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping , 2001, IEEE J. Solid State Circuits.

[12]  Un-Ku Moon,et al.  A 6b stochastic flash analog-to-digital converter without calibration or reference ladder , 2008, 2008 IEEE Asian Solid-State Circuits Conference.