An FPGA-based computation model for blocked algorithms
暂无分享,去创建一个
[1] Ken Kennedy,et al. Automatic blocking of QR and LU factorizations for locality , 2004, MSP '04.
[2] Pedro C. Diniz,et al. Automatic synthesis of data storage and control structures for FPGA-based computing engines , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).
[3] Pedro C. Diniz,et al. Performance and area modeling of complete FPGA designs in the presence of loop transformations , 2004, IEEE Transactions on Computers.
[4] Pedro C. Diniz,et al. Application-specific external memory interfacing for fpga-based reconfigurable architecture , 2004 .
[5] Pedro C. Diniz,et al. Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).
[6] Christian H. Bischof,et al. A block QR factorization algorithm using restricted pivoting , 1989, Proceedings of the 1989 ACM/IEEE Conference on Supercomputing (Supercomputing '89).
[7] Charles L. Lawson,et al. Solving least squares problems , 1976, Classics in applied mathematics.
[8] Pedro C. Diniz,et al. Performance and area modeling of complete FPGA designs in the presence of loop transformations , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..
[9] Wayne Luk,et al. Pipeline vectorization for reconfigurable systems , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).
[10] Robert A. van de Geijn,et al. Parallel out-of-core computation and updating of the QR factorization , 2005, TOMS.