Predictive compact models for two key variability sources in FinFET technology, the gate edge roughness (GER) and Fin edge roughness (FER), are proposed for the first time, and integrated into industry standard BSIM-CMG core model. Excellent accuracy and predictivity is verified through atomistic TCAD simulations. The inherent correlations between the variations of device electrical parameters are well captured. In addition, an abnormal non-monotonous dependence of variations on Fin-width is observed, which can be explained with the newly found correlation between random variations and electrostatic integrity in FinFETs. The impacts of GER and FER on circuits are efficiently predicted for 16/14nm node and beyond, providing helpful guidelines for variation-aware design and technology process development.