The demand for Static Random Access Memory (SRAM) is increasing with large use of SRAM in system on-chip and high performance VLSI circuits. This paper focuses on the dynamic power dissipation during the Write operation in CMOS SRAM cell. Charging and discharging of bit lines consume more power during the Write “1” and Write “0” operation. Today’s microprocessors are very fast and require fast caches with low power dissipation. In this paper the 8T SRAM cell, includes two more trail transistors in the pull down path for proper charging and discharging the bit lines. Due to this it consumes less power, delay and short circuit power during write operation. The 8T SRAM cell designed and optimized using Tanner Tool. Schematic of the SRAM cell is designed on S-Edit and Net list Simulation done by using T-Spice and waveforms are analyzed through W-EDIT. The circuit is characterized by using the 130nm technology which is having supply voltage of 1.5volt.The results of 8T SRAM cell is compare with conventional 6T SRAM. This paper optimize low power 8T SRAM which reduce power and delay during Write operation
[1]
Ron Ho,et al.
Low-power SRAM design using half-swing pulse-mode techniques
,
1998,
IEEE J. Solid State Circuits.
[2]
Rahul Rishi,et al.
Asymmetric SRAM- Power Dissipation and Delay
,
2011
.
[3]
Lee-Sup Kim,et al.
A low-power SRAM using hierarchical bit line and local sense amplifiers
,
2005,
IEEE J. Solid State Circuits.
[4]
M. Ukita,et al.
A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's
,
1993
.
[5]
Dake Liu,et al.
Power consumption estimation in CMOS VLSI chips
,
1994,
IEEE J. Solid State Circuits.
[6]
J. Meindl,et al.
The impact of intrinsic device fluctuations on CMOS SRAM cell stability
,
2001,
IEEE J. Solid State Circuits.
[7]
James Tschanz,et al.
Parameter variations and impact on circuits and microarchitecture
,
2003,
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).