Toward Scalable Superconducting Quantum Computer Implementation

In the recent years, the development of quantum computers has been accelerated. In parallel with the research in universities, the enormous efforts in industry such as in Google, IBM and Intel have dramatically increased the number of integrated quantum bits (qubits). It is anticipated to realize quantum computers exceeding a few hundred qubits in several years. As of June 2018, Google has realized quantum computers up to 22 qubits [1] and demonstrated its operation with the lowest error rate of 1% per gate in their 9-qubits device [2]. IBM has also realized quantum computers up to 20 qubits; those up to 16 qubits are open to the world through a free cloud service, and the 20-qubit one is for commercial use [3]. While those prototype quantum computers are highlighted in daily news articles, it may require some time to realize a fully fault-tolerant quantum computer. In this paper, we briefly review the basic operation principle of a qubit, and introduce a hardware architecture of superconducting quantum computers and its implementation. Furthermore, we discuss the technologies required for medium-scale quantum computers which provide several error-tolerant “logical” qubits with more than ten thousands of physical qubits and with the error rate below 0.1% [4].

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