Qualitative Analysis of 2-bit CMOS Magnitude Comparator and GDI Magnitude Comparator using FinFET Technology (18nm)

Magnitude Comparators are extensively used in digital systems to perform operations such as Equality, Less than or Greater than thus, they can be used in a variety of application such as in sorting algorithms, priority encoding and taking, password and biometric verification and many more so, The proposed research work has qualitatively analysed the CMOS logic magnitude comparator and GDI logic comparator (both of them are 2-bit) which is implemented using 18nm FinFET technology, Here our primary objective is to optimize this logic circuitry so an experimental analysis is conducted comprising parameters such as propagation Delay, Power, Area and Power-Delay-Product (PDP). All experimental analysis is done using Cadence Virtuoso (cds-ff-mpt library is used for FinFET 18 nm).