Implementing Control Algorithms with FPGAs

The chapter is devoted with FPGA-based implementing control algorithms represented using the language of graph-schemes of algorithms. We use models of Mealy and Moore finite state machines (FSM) to design the circuits of control units. We start from single-level FSM circuits implemented using look-up table (LUT) elements and/or embedded memory blocks (EMB). These methods are illustrated using standard benchmark FSMs. Next, the methods of structural decomposition are discussed. We discuss how to reduce hardware using the replacement of logical conditions, encoding the collections of microoperations, encoding the terms, and transformation of objects. We show how to use the pseudoequivalent states for optimization of logic circuits of Moore FSMs. The third section is devoted to hardware reduction of Moore FSMs targeting the replacement of logical conditions. At last, we discuss how to optimize hardware replacing state registers by state counters. The discussed methods target control units based on models of Moore FSMs.

[1]  Anurag Tiwari,et al.  Saving power by mapping finite-state machines into embedded memory blocks in FPGAs , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[2]  Alexander Barkalov,et al.  Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM , 2007, Int. J. Appl. Math. Comput. Sci..

[3]  Alexander Barkalov,et al.  Evolution of Programmable Logic , 2009 .

[4]  Alexander Barkalov,et al.  Logic Synthesis for Compositional Microprogram Control Units , 2008, Lecture Notes in Electrical Engineering.

[5]  Svetlana Yanushkevich,et al.  Introduction to Logic Design , 2008 .

[6]  Clive Maxfield.  FPGAs: Instant Access , 2008 .

[7]  Alexander Barkalov,et al.  Design of EMB-Based Moore FSMs , 2017 .

[8]  Alexander Barkalov.  DESIGN OF MEALY FINITE-STATE MACHINES WITH THE TRANSFORMATION OF OBJECT CODES , 2005 .

[9]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[10]  Alexander Barkalov,et al.  Logic Synthesis for FSM-Based Control Units , 2009, Lecture Notes in Electrical Engineering.

[11]  Valery Sklyarov.  Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs , 2000, FPL.

[12]  L. A. Titarenko,et al.  Structural decomposition as a tool for the optimization of an FPGA-based implementation of a mealy FSM , 2012 .

[13]  Alexander Barkalov,et al.  Synthesis and Optimization of FPGA-Based Systems , 2014 .

[14]  Mariusz Rawski,et al.  The Influence of Functional Decomposition on Modern Digital Design Process , 2005 .

[15]  Ian Elliott,et al.  FSM-Based Digital Design Using Verilog HDL: Minns/FSM-Based Digital Design Using Verilog HDL , 2008 .

[16]  Clive ldMax rd Maxfield,et al.  The design warrior's guide to FPGAs , 2004 .

[17]  Russell Tessier,et al.  FPGA Architecture: Survey and Challenges , 2008, Found. Trends Electron. Des. Autom..

[18]  Dariusz Kania,et al.  Area and speed oriented synthesis of FSMs for PAL-based CPLDs , 2012, Microprocess. Microsystems.

[19]  Ian Elliott,et al.  FSM-based Digital Design using Verilog HDL , 2008 .

[20]  Alexander Barkalov,et al.  Hardware reduction for RAM-based Moore FSMs , 2014, 2014 7th International Conference on Human System Interactions (HSI).

[21]  Dariusz Kania,et al.  Finite State Machine Logic Synthesis for Complex Programmable Logic Devices , 2013 .

[22]  Alexander Barkalov,et al.  Logic Synthesis for FPGA-Based Finite State Machines , 2015 .

[23]  A. A. Barkalov.  Principles of logic optimization for a moore microprogrammed automaton , 1998 .