An ASIC implementation of phase correlation based on run-time reconfiguration technique

In this paper, we present an application-specific LSI that is designed using a run-time reconfiguration technique. The implemented algorithm is phase correlation. The calculation of phase correlation includes Fast Fourier Transform (FFT) followed by Inverse Fast Fourier Transform (IFFT). We have developed a dual-decimation butterfly module that can be self-reconfigured, at run-time, to be either decimation-in-time (DIT) or decimation-in-frequency (DIF). By sharing the common parts between the DIT and DIF butterfly modules, the dual-decimation butterfly module can reduce the logic size to about half. DIT-mode is used for FFT and DIF-mode is used for IFFT. No data reordering, such as natural-to-reverse or reverse-to-natural conversion, between FFT and IFFT is necessary. As a consequence, the amount of intermediate frame buffers and the number of memory accesses are significantly reduced.

[1]  K. Kobayashi,et al.  An image processor implementing algorithms using characteristics of phase spectrum of two-dimensional Fourier transformation , 1999, ISIE '99. Proceedings of the IEEE International Symposium on Industrial Electronics (Cat. No.99TH8465).

[2]  Thomas S. Huang,et al.  The importance of phase in image processing filters , 1975 .

[3]  Jonathan Rose,et al.  Measuring the Gap Between FPGAs and ASICs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  L. Karnan,et al.  A 100 MHz 7.84 mm^2 31.7 msec 439 mW 512-Point 2-Dimensional FFT Single-Chip Processor , 2004 .

[5]  Koji Kotani,et al.  A 3.7×3.7mm2 310.9mW 105.2msec 512×512-Pixel Phase-Only Correlation Processor , 2005, J. Robotics Mechatronics.

[6]  C. D. Kuglin,et al.  The phase correlation image alignment method , 1975 .

[7]  B. N. Chatterji,et al.  An FFT-based technique for translation, rotation, and scale-invariant image registration , 1996, IEEE Trans. Image Process..

[8]  Bevan M. Baas,et al.  A low-power, high-performance, 1024-point FFT processor , 1999, IEEE J. Solid State Circuits.

[9]  K. Kobayashi,et al.  Pixel-and-column pipeline architecture for FFT-based image processor , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[10]  T. Higuchi,et al.  High-Accuracy Subpixel Image Registration Based on Phase-Only Correlation , 2003, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..