Introducing a technology index concept and optimum performance design procedure for single-electron-device based circuits

Single electron devices (SEDs) are utilized in designing many logic gates; however, in most cases the examination of the circuits is limited to a DC analysis that only indicates the correct performance of the circuits' logic function. This paper focuses mainly on the issue of optimization. In this regard, comparison of different designs is needed, but it is not possible to compare two different designs unless they both belong to a single technology or can be scaled to a same technology. So, we first introduce a technology index for SEDs, which allows meaningful comparisons between various designs of different technologies. Then, we describe a method for scaling these designs into a single identical technology, and clarifying the relations between the involved concepts. Using two examples, we explain an optimum design method for digital logic gates based on SEDs. Finally, the results of these two examples are presented and compared with the original designs. The comparison showed that all the three major performance features, including lower bit error rate, higher operation frequency, and higher temperature operation are improved in the proposed optimized design.

[1]  C. Lageweg,et al.  Design methodology for single electron based building blocks , 2005, 5th IEEE Conference on Nanotechnology, 2005..

[2]  Yoshihito Amemiya,et al.  Single-Electron Majority Logic Circuits , 1997 .

[3]  Y. Takahashi,et al.  Silicon Single-electron Devices for Logic Applications , 2002, 32nd European Solid-State Device Research Conference.

[4]  Yasuo Takahashi,et al.  Multigate single-electron transistors and their application to an exclusive-OR gate , 2000 .

[5]  Siegfried Selberherr,et al.  SIMON-A simulator for single-electron tunnel devices and circuits , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Ioannis Karafyllidis,et al.  Design and simulation of a nanoelectronic single-electron Control - Not gate , 2006, Microelectron. J..

[7]  C. Lageweg,et al.  Buffer design trade-offs for single electron logic gates , 2005, 5th IEEE Conference on Nanotechnology, 2005..

[8]  Konstantin K. Likharev,et al.  Single-electron devices and their applications , 1999, Proc. IEEE.

[9]  S.E. Rehan.  A Novel Half-Adder Using Single Electron Tunneling Technology , 2007, 2007 2nd IEEE International Conference on Nano/Micro Engineered and Molecular Systems.

[10]  K. Matsumoto.  STM/AFM nano-oxidation process to room-temperature-operated single-electron transistor and other devices , 1997, Proc. IEEE.

[11]  Yong-Bin Kim,et al.  SET-based nano-circuit simulation and design method using HSPICE , 2005, Microelectron. J..

[12]  K. Matsumoto,et al.  Room temperature Nb/Nb oxide-based single-electron transistors , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[13]  Tetsuya Asai,et al.  A majority-logic device using an irreversible single-electron box , 2003 .

[14]  Ioannis G. Karafyllidis,et al.  A single-electron half-adder , 2002 .

[15]  Ioannis G. Karafyllidis,et al.  A single-electron XOR gate , 2001 .

[16]  Transient Response of Single-electron Devices and Their Time Constants , 2011 .