Designing Efficient Online Testable Reversible Adders With New Reversible Gate
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[1] P. Oscar Boykin,et al. Reversible fault-tolerant logic , 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).
[2] Tommaso Toffoli,et al. Reversible Computing , 1980, ICALP.
[3] J. Hayes,et al. Fault testing for reversible circuits , 2003, Proceedings. 21st VLSI Test Symposium, 2003..
[4] Parag K. Lala,et al. Reversible-logic design with online testability , 2006, IEEE Transactions on Instrumentation and Measurement.
[5] John P. Hayes,et al. Fault testing for reversible circuits , 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] Charles H. Bennett,et al. Logical reversibility of computation , 1973 .
[7] Rolf Landauer,et al. Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..
[8] P. K. Lala,et al. Online testable reversible logic circuit design using NAND blocks , 2004 .
[9] T. Toffoli,et al. Conservative logic , 2002, Collision-Based Computing.