A Dynamically Reconfigurable Automata Processor Overlay

This paper describes a design for a parameterizable automata processor overlay and a placement algorithm required for its support software. The resulting framework serves as both an open-source alternative to Micron's Automata Processor (AP) and as an experimental testbed for exploration of architectural tradeoffs. An automata processor is a processor-in-memory architecture designed to recognize patterns in streaming data. Our framework takes a description of a nondeterministic finite automata (NFA) described in Micron's ANML language and uses instantiated JTAG sources to configure the on-chip RAM and programmable interconnect of the overlay programmed onto an FPGA. Like the Micron AP, our design is comprised of an array of interconnected state transition elements (STEs). While our STE design is equivalent to that of the Micron AP, our overlay uses a simpler, non-switched interconnect based on pairwise gated connections. This interconnect design creates a constraint satisfaction problem when mapping logical states to the physical STEs. In this paper, we explore the impact of tradeoffs in the interconnect architecture as it relates to a Stratix 5 GX target device and we describe and evaluate an algorithm for STE placement with respect to the ANMLZoo benchmark suite. As far as the authors know, this is the first example of an FPGA-based automata processor overlay.