RoSA: a reconfigurable stream-based architecture

The increase of stream-based applications complexity has demanded hardware more flexible and able to reaching higher performance. Reconfigurable architectures have been showed significant progresses in exploiting the parallelism of these applications. This paper presents RoSA, a coarse-grained reconfigurable architecture that combines compilation techniques and hardware reuse to accelerate the execution of stream-based applications. The results showed that RoSA achieved performance gains of more than 74% over the code that can be executed concurrently and 55% of the total cost of the applications.

[1]  Gregory K. Wallace,et al.  The JPEG still picture compression standard , 1992 .

[2]  Prithviraj Banerjee,et al.  A C compiler for a processor with a reconfigurable functional unit , 2000, FPGA '00.

[3]  Mario J. Gonzalez,et al.  FFT on reconfigurable hardware , 1995, Optics East.

[4]  Cesare Alippi,et al.  A DAG-Based Design Approach for Reconfigurable VLIW Processors , 1999, DATE.

[5]  Reiner W. Hartenstein,et al.  Coarse grain reconfigurable architecture (embedded tutorial) , 2001, ASP-DAC '01.

[6]  William J. Dally,et al.  Media processing applications on the Imagine stream processor , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[7]  Laura Pozzi Methodologies for the Design of Application-Specific Reconfigurable VLIW Processors , 2000 .

[8]  Marco Platzner Reconfigurable computer architectures , 1998 .

[9]  Kees A. Vissers,et al.  Parallel processing architectures for reconfigurable systems , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[10]  L. Pozzi Compilation Techniques for Exploiting Instruction Level Parallelism , a Survey , 1999 .

[11]  B. Ramakrishna Rau,et al.  Instruction-level parallel processing: History, overview, and perspective , 2005, The Journal of Supercomputing.

[12]  Andreas Moshovos,et al.  CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[13]  Michael Herz,et al.  Memory addressing organization for stream-based reconfigurable computing , 2002, 9th International Conference on Electronics, Circuits and Systems.

[14]  Sergio Bampi,et al.  Accelerating a multiprocessor reconfigurable architecture with pipelined VLIW units , 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).

[15]  Wayne Luk,et al.  Reconfigurable computing: architectures and design methods , 2005 .

[16]  Seth Copen Goldstein,et al.  PipeRench: a co/processor for streaming multimedia acceleration , 1999, ISCA.

[17]  S. Bampi,et al.  Pipelined fast 2D DCT architecture for JPEG image compression , 2001, Symposium on Integrated Circuits and Systems Design.

[18]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[19]  Reiner W. Hartenstein Coarse grain reconfigurable architectures , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[20]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[21]  Viktor K. Prasanna,et al.  Seeking Solutions in Configurable Computing , 1997, Computer.

[22]  Massimo Violante,et al.  ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications , 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

[23]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Re-configurable Architecture , 2000 .